asicNorth – Comprehensive and Innovative VLSI Design Solutions

• Mixed-Signal Cores
• Off-chip Drivers and Receivers
• Voltage Regulators
• Standard Cell Libraries
• Phrase Locked Loops

IP Conversion

• Migrate Existing Designs to New Technologies
• Optimize Performance, Power, Cost
• Obsolete Parts

Full Custom Design

• Methodology Development
• EDA View Generation
• Automated and Full Custom Layout
• Circuit Simulation and Mixed-Signal Verification

• Architecture
• System-on-chip Building Blocks
• Interfaces
• Test Chip Assembly
• System Verilog
• Questa™ Vanguard Partner

ASIC Processing

• Synthesis
• Design For Test
• Static Timing Analysis
• Formal Equivalence
• Back Annotated Delay Simulations

Physical Design

• Full Physical Design Flow Expertise from RTL to GDSII down to 32nm
• Automated and Full Custom Options
• Route Fixing with Noise Analysis
• Clock Tree Management, Clock Gating, Balancing, Skew Reduction and Short Insertion Delays
• Full Chip Floor Planning
• Timing Closure with Noise Fixing

• IP Embodiments
• ASIC Infrastructure (Libraries, I/Os,Fabrics)
• Complex Design IP of Various Forms (Analog and Digital Cores, Memories)
• Semiconductor-Based End Product

Test Various

• Aspects of the Design
• Feature Validation
• Parametric Characterization such as I/O Timings, Power, Performance, Jitter, Standby Current
• Intellectual Property Characterization across Process, Temperature and Voltage Corners

Develop the Infrastructure

• Required to Achieve Testing Goals
• Performance Test Chips with Embedded
• Characterization Structures
• Test Boards for Functional Validation and Characterization